Alternative Types of Embedded Memories Tailored for Ultra-Low Power and Error-Resilient VLSI Systems-on-Chip

Abstract:

This talk surveys two recent and persisting trends in the field of very large scale integration (VLSI) system-on-chip (SoC) design with emphasis on the design and optimization of embedded memories. On the one hand, the advantages and drawbacks of ultra-low voltage (ULV) / ultra-low power (ULP) VLSI systems, exhibiting circuit operation it the near-threshold or even in the subthreshold regime, often targeted at biomedical applications or at wireless sensor networks, are reviewed. Such systems require ultra-low leakage power, as they often need to run for several years on a single battery charge, and need to be highly reliable, especially in the biomedical application field. Designing and integrating a large amount of embedded memories unifying these properties is a major challenge. On the other hand, the emerging class of error-resilient, high-performance VLSI systems exhibits completely different properties. Instead of ensuring 100% correct circuit operation by conservative design and expensive design margins, a small amount of circuit failures is tolerated, detected, and corrected for at system level, thereby allowing fast, over-clocked circuit operation or energy savings through slightly excessive voltage down-scaling. Wireless communications channel decoders, primarily built to deal with channel-induced noise, are an intuitive example of such error-resilient VLSI systems, while many error detection and correction schemes have recently been presented for microprocessors, as well.

As embedded memories account for an increasingly dominant power and area share of virtually all modern VLSI systems, we aim at implementing alternative types of embedded memories, specifically designed for and exploiting special characteristics of ULV/ULP systems on the one hand, and error-resilient VLSI systems on the other hand. In a first line of research, gain-cell based embedded dynamic random-access memories (eDRAMs) are identified as an interesting alternative to conventional static random-access memories (SRAMs). Such gain-cell eDRAMs can be built from multi-level cells for high storage density and speed, at the price of dramatically reduced reliability. Alternatively, this type of embedded memory can be optimized for high robustness even at ultra-low operating voltages where the access bandwidth is severely degraded. As a second line of research, standard-cell based memory (SCM) architectures are presented as a straightforward approach to small, distributed embedded memory arrays which merge seamlessly with and operate at the same voltage as the core logic, be it in the subthreshold domain or at nominal voltage. The customization of a single standard-cell can render these SCM arrays either highly energy-efficient for use in ULV/ULP systems, or competitively small and fast for use in error-resilient VLSI systems. As a last line of research, non-volatile flip-flop architectures which integrate emerging ReRAM devices ("memristors") on top of CMOS chips, thereby enabling instant-on computing systems and sensor nodes with zero-leakage sleep states are presented. For the first time, we operate these non-volatile memory elements at subthreshold voltages and demonstrate robust operation even with parametric variations in both the ReRAM decices and MOS transistors.

 

תאריך: 
06/03/2013 - 15:00
מרצה: 
Pascal Meinerzhagen
דוא"ל להרשמה: 
Affiliation: 
EPFL
מיקום: 
building 1103, Room 329