On-Chip Analog Readout Circuit for Planar-Hall-Effect-Magnetic-RAM
Modern IC industry is starving for new devices that will make the leap and meet the needs of more demanding applications than ever before. This is the case in many fields, including imaging and memory IC’s and SOC’s that incorporate them. The needs for an increasingly large arrays, with better figure of merits, can only be met through process improvement for a limited time. Keeping this momentum mandates the development of new types of devices that will surpass the devices in current use. This process is easily seen in the field of on-chip memories, where the list of demands keeps on growing; with higher density, lower power, higher speed, and non-volatility accounting for just a portion of that list. In an effort to meet those needs, both the industry and academia have been working on improved variants of the industry standard memories such as Static Random Access Memory (SRAM); as well as coming up with new memory technologies such as the new forms of Magnetic-RAM (MRAM).
In this race to come up with the devices for the next generation, many challenges are encountered, throughout the process of development, manufacturing, and integration within the IC’s. In many cases, device development shows promise, and lab measurements of a single device can meet the expectations and even surpass them. However, integration within current IC’s is a whole other challenge that must be handled. Minding the gap between the electrical interfaces of these novel devices, and existing CMOS circuitry is a challenge that must be met, within a sufficiently low “system budget”. Otherwise the added area/power/cost of this “adaptor” circuitry will render the new device unworthy.
The work presented in this thesis is aimed at meeting this challenge. To achieve this goal, a novel type of MRAM, the Planar-Hall-Effect-MRAM (PHE-MRAM) is chosen for its unique properties; and a complete readout circuit is designed to allow integration of this novel type of memory on chip. The work includes a discussion of the circuit requirements set by this novel type of memory, along with a detailed design process of a unique readout circuit topology to meet these requirements. A detailed analytical derivation of circuit operation and its limitations is carried out, followed by simulation results to support the discussion. A test chip with the proposed readout circuit design is taped out, and detailed measurement results are provided.
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