VLSI lab Student Projects
VLSI Lab offers undergraduate students of 4th year four types of advanced projects:
1. Design and implementation of VLSI chip on an FPGA Development Board - Front-End Design activity.
2. Implementation of the FPGA-verified VLSI chip as an ASIC ready for FAB (GDSII) - Back-End Design activity.
3. System Integration - incorporating available proven designs, into a Systen-On-FPGA or SOC.
4. Supporting Software - Software Development Kits, Compilers, Device Drivers, etc.
The above activities involve full functional core/chip design from architecture up to physical layout implementation
or full system integration. Collaboration between project teams, are often exercised.
A Project may involve 2-3 students for a year. The design is performed employing industry standard CAD tools.
Tight supervision is provided to the students on a weekly basis while they go through the entire design,
implementation and verification process.
Devices
Animation Graphic Engine
16bit RISC µController
Protocol-aware DMAC
USB2.0 Protocol Engine
USB2.0 SDK and Compiler
Decimal Floating Point Unit
Optical Transport Network (OTN) Framer Software
Optical Transport Network (OTN) Framer Hardware
Ray Tracing Algorithm Engine
DFP Arithmetic Modules Implementation
Enhanced MIPS Processor
Systems
USB 2.0 Device Development System
GOK System Integration
Optical Transport Network (OTN) System Integration
Animation Graphic Engine
2009 Exceptional Project
Yair Naperstak
Idan Shtainmet
Lee Cohen
1. Introduction
The Animation Graphic Engine (AGE) is a three-dimensional (3D) Computer Graphics Hardware Accelerator, performing basic Animation operations (3D graphics manipulation) and pixel-related backend Rasterization operations, the basic steps required to render a polygon-based (Triangles) 3D graphics model generating photo-realistic images in real time. 3D graphics pipeline polygon-based 3D graphic rendering is the process of converting the geometric description of a 3D model (or a virtual world) to a two-dimensional image (a 2D array of picture elements or pixels) that can be displayed on a computer monitor. Each pixel represents a color value consisting of red, green, and blue (RGB) components.
2. System-level description
Commonly-used Computer graphics subsystem Architecture consists of host CPU-based Geometry Processing and dedicated Hardware Accelerator for Animation and Rasterization. The AGE can be used by Desktop/Laptop Computers as well as by Game Consoles, PDAs or Mobile Smart-Phones. It can be embedded as an integral part of the system Hardware or be implemented as an attached USB2.0 Device. Graphic Application like OpenGL, defines the object to be displayed, both its geometry and color. Performs triangulation of its surface, calculating the vertices edges and the triangles that comprise the object. Assigns colors to every vertex. Sends the following initial data to the USB port:
- List of vertices comprising the triangulated object’s surface.
- List of triangles given by their enclosing edges in cyclic order and their RGB color.
- An outward normal vector to every triangle (set to unit length).
- A box of the real world where the object exists, given by their coordinates.
- The screen view port where the object should be displayed, given by the window location within the screen (in pixels).
- A light unit vector.
- Background RGB colors for the frame buffer.
The Application then performs an animation session where the above object with its world box are moving and rotating in space according to some externally defined trajectory. The animation related data is transferred to the USB port at a rate of and it comprises of a matrix representing object’s new position and an indicator which one of the projection planes XY, XZ or YZ will be displayed in the screen view port. The AGE, following the completion of the initialization stage, performs the animation at a rate of by applying hardware operations whose mathematical definitions and hardware implementation are described subsequently. The result of every animation step is the contents of a Frame Buffer comprising of the predefined screen view port's pixels associated with RGB colors each. The Frame Buffer data is addressed directly to the graphics board of the Host Computer.
3. Project targets and problem at hand
The goal of the project was to develop and implement a Hardware Core that can perform the basic rendering operations defined for handling polygon-based three dimensional (3-D) graphic images. Computer graphics subsystems today are based on very fast multiple compute cores, having common memory pool executing the rendering operations in floating point. This architecture is power-hungry, requires cooling systems and suited for wall-plugged Devices. There is a lack of low power; battery operated graphical cores that can serve Mobile Game Consoles, Personal Digital Assistant s and Smart-Phones. This project is a good start for a solution to the "mobile graphics" syndrome. Continuation along this track will eventually provide a quality solution to the problem.
16bit RISC µController
Roi Shidlovski
David Shlomov
Tailored to perform as the Control Core of a Vendor-Specific, or any Standard-Defined Class, USB2.0 Device, based mostly on Hardware implemented Application Cores (Accelerators).
The RISC µController instruction Set is divided into 3 main groups:
- Control-transfer class
- ALU class
- Specialized I/O Instructions
Also included:
- Memory-mapped I/O
- Direct indexed commands
- Pipeline Architecture for higher throughput / better performance
- ALU, Register File, External Program Memory, I/O Registers
- External synchronous SRAM and ROM memory devices Interfaces
The µController includes a Bus Interface Unit (BIU) that supports access to/from external synchronous SRAM, ROM/EEPROM and DRAM memory devices. It also supports System Bus Arbitration with external Master, like DMAC and System Interrupts.
Protocol-aware DMAC
The DMAC is an integral part of a vendor-specific USB2.0 Device Controller System. DMAC function, within the system, is to transfer data from/to the USB2.0 Protocol Engine (PE) RX/TX Packet Buffers to/from Device Controller Endpoints, under the Protocol Engine control. The DMAC is a system bus master, being programmed as peripheral device for required functionality by the system µController at system boot time. The joint functionality of the Protocol Engine and the DMAC, offload communication tasks from the system Controller. The DMAC is capable of performing bytes scatter-gather, supporting system data bus up to 48bits (6 bytes) and up to 24bits address bus (16Mbytes address range).
USB2.0 Protocol Engine
2010 Exceptional Project
Razi Hershenhoren
Omer Reznik
The Protocol Engine supports the Device side of a connection between a USB host computer and vendor-specific intelligent peripheral. It supports control, isochronous, bulk and interrupt transfer types between a local bus and a Universal Serial Bus (USB). The Protocol Engine, processes Fast and High Speed USB 2.0 packet-level Link-Layer Protocol tasks in Hardware.
USB2.0 SDK and Compiler
2010 Exceptional Project
Alon Fital
Chen Hajaj
Software Development Suite, running under Windows XP Operating System.
Includes:
- Development Environment for generating Device Descriptor Tables
- Host Driver for the Device Controller, based on WinUsb
- Compiler for the Device Controller’s 16bit RISC µController
An intuitive Application Programming Interface (API) for the development of Hi Speed USB 2.0 Device Controller Applications. Supports single configuration and up to four interfaces. The SDK supports Endpoint 0 for Enumeration (via Control transfer type), enables configuration of Endpoints and creating the appropriate Descriptor Tables for a specific application. Each of up to 15 IN and 15 OUT endpoints, for any of the 4 supported interfaces, can be individually configured to either Interrupt or Bulk transfer type and for Buffer (max. packet) size. The µController’s Assembler, enables generating the machine code for the µController, needed for configuration of the Device protocol-aware DMA Controller and the Protocol Engine. The Host Driver enables the Application Program, running on the Host, to control and monitor the Vendor-specific USB2.0 Device behavior and functionality. A Test Suite, running on the Host, is created for the specific-configured Device Controller and used to verify correct operation, USB 2.0 Protocol compliance and interoperability.
Decimal Floating Point Unit2011 Exceptional Project
Ariel Burg
Hillel Rosensweig
Decimal Floating Point Calculations are important in many commercial applications including financial analysis, banking, tax calculation, currency conversion, insurance, and accounting. Due to the importance of decimal arithmetic in commercial applications and the potential speedup achievable microprocessors supporting decimal floating-point (DFP) arithmetic are now available. Further, specifications for decimal arithmetic have been added to the updated IEEE – 754-2008 Standard for Floating-Point Arithmetic. This standard provides a method for computation with floating-point numbers that will yield the same result whether the processing is done in hardware, software, or a combination of the two. The results of the computation will be identical, independent of implementation, given the same input data. Errors, and error conditions, in the mathematical processing will be reported in a consistent manner regardless of implementation. .
In this project a hardware decimal floating-point unit that complies with IEEE 754 specifications for decimal Floating point has been designed, implemented and tested.
Optical Transport Network (OTN) Framer Software
Shai Ungar
Ohad Benjamin
The Project team implemented the Framer Processing Algorithm in Software, adhering to the newly introduced Optical Transport Network (OTN) ITU-T G.709 Communication Standard. The Framer Processing Algorithm has been implemented on a PC and correct behavior has been analyzed by simulation (Creating Frames and transferring input files to output files). The Framer supports Two Hierarchical levels (2 Buffers --> OTN Frames Buffer).
A System Integration Test Environment, has been developed as well, to ease future Framer System Integration.
OTN Framer Software project book
Optical Transport Network (OTN) Framer Hardware
Golan Orlev
Igal Karlinsky
The Project team implemented in Hardware, Data and Headers routing of the OTN Packets and the Hardware Accelerator, Aligner and Scrambler of the Framer, adhering to the newly introduced Optical Transport Network (OTN) ITU-T G.709 Communication Standard.
OTN Framer Hardware project book
^ TopRay Tracing Algorithm Engine
Ori Millo
Aviner Fishhof
Ray Tracing is a relatively new graphic technique for rendering 3-D images with complex lighting models to achieve photographic realism. Ray Tracing detects visibility, transparency, shadows, illumination effects, and generates perspective views. Computational intensive.
Design of an efficient, low power, Hardware Accelerator could lower the cost of Ray Tracing implementation.
Literature: Ray Tracing from the Ground Up. Author - Kevin Suffern. Publishing - A K Peters Ltd. Wellesley, Massachusetts.
^ TopDFP Arithmetic Modules Implementation
Moriya Klimanovsky
Daniel Babitzki
1. Introduction1. Introduction Design and implementation of Decimal Floating Point Arithmetic Modules.
Decimal multiplication is important in many commercial applications including financial analysis, banking, tax calculation, currency conversion, insurance, and accounting. Due to the importance of decimal arithmetic in commercial applications and the potential speedup, a basic system supporting decimal floating-point (DFP) arithmetic has been developed in BIU's VLSI lab.
In this project, we will design, analyze performance, prove correctness and implement a decimal multiplier and a decimal divider. These arithmetic modules should comply with IEEE 754 specifications for decimal arithmetic.
Enhance MIPS Processor
2014
Enhance the capabilities of the current basic 32bit MIPS by extending its instruction set, adding stack and cache, interrupt support, write Assembler Compiler that handle data hazards in the processor pipeline and Interrupt Service Routines (ISR).
This extended MIPS will be used for exercises and research.
Option for adding smart multipliers (Arithmetic's Course students).
^ Top
USB 2.0 Device Development System
1. Introduction
The USB2.0 Device Development System, to be integrated in BIU VLSI LAB, will have the following major building blocks:
- Reduced Instruction Set Computer (RISC) µController
- Protocol Engine (PE)
- Protocol-aware Direct Memory Access Controller (DMAC)
- Software Development Kit (SDK) and Compiler
Employing the USB2.0 Device Development System and a commercial mixed-signal USB 2.0 Transceiver chip (PHY), a Vendor-Specific or any Standard-Defined USB2.0 Device Class, can be implemented. Design Engineer or a Design Team, defines the functionality of a USB2.0 Device to fulfill specific requirements. The design includes writing Device Specifications and Programming Model (including detailed Descriptor Tables), selecting a commercial mixed-signal USB 2.0 Transceiver chip (PHY), Low Dropout Voltage Regulator (LDO), other peripheral components (Device Specific Logic) and storage (memory sub-system). The user-friendly SDK is used to develop the code for the RISC µController. The code is compiled for the RISC µController and programmed into a non-volatile memory and is being executed by the RISC µController as soon as the Device is attached to the USB connector (power is applied via the USB BUS pins V+/V-) and Reset is deactivated. The Transceiver chip handles the Physical and bit-level LINK Protocol Layers of the USB 2.0 Communication Model. It is a mixed-signal device, containing elements like A2D, D2A and a 480MHz PLL. The Protocol Engine, a memory-mapped Peripheral Device, enables the µController to handle even complex Device’s Application-Level Tasks by processing USB 2.0 packet-level Link-Layer Protocol tasks in Hardware. The interface between the USB 2.0 Transceiver chip (PHY) and the Protocol Engine (The Serial Interface Engine Block (SIE)), is defined by the UTMI (USB2.0 Transceiver Macrocell Interface) Standard. Both Transceiver chip and Protocol Engine support high-speed (480 Mbps) and full-speed (12Mbps) signaling bit rates.
2. System Block Diagram
3. Functional Description
3.1. 16bit RISC µController
Refer to section Devices
3.2. Protocol-aware DMAC
Refer to section Devices
3.3. Protocol Engine
Refer to section Devices
3.4. USB 2.0 Transceiver chip (PHY)
The PHY is basically a Serializer-Deserializer (SERDES), bit stuffer/un-stuffer and NRZI encoder/decoder, which also handles the low level USB protocol and the signaling task. While transmitting data, the PHY serializes data and generates SYNC and EOP fields. It also performs needed bit stuffing and NRZI encoding. Likewise, while receiving data, the PHY de-serializes incoming data, stripping SYNC and EOP fields and performs bit un-stuffing and NRZI decoding. Handles Speed Enumeration, Suspend/Resume, Synchronization. A commercial available USB 2.0 Transceiver chip is used
3.5. Memory Sub-System
The ROM or EEPROM is used as the Program Memory for the µController. The SRAM and the DRAM are used for both the System and the Application. The Application might include the SRAM and DRAM (and Register Files if needed).
3.6. USB2.0 SDK and Compiler
Refer to section Devices
Graphics-On-Key GOK System Integration
Eddy Kiselman
Eyal Tzadok
1. Introduction
Graphic-On-Key (GOK) project target is to deliver a low power, USB2.0 Graphic Device, to be used as an Animation Engine for Mobile Systems like Game Stations or Mobile Computing Systems. The already designed, implemented and functionally verified Animation Graphic Engine (AGE) Core, serves as a USB2.0 Device Function Core. The AGE performs the basic steps required to render a polygon-based 3D graphics model (picture), employing a graphics pipeline to turn a 3D model (or a virtual world) to a two-dimensional image (a 2D array of picture elements or pixels) that can be displayed on a computer monitor. A USB2.0 Protocol Engine (PE) processes USB 2.0 Link Layer Protocol in Hardware and supports high-speed (480 Mbps) and full-speed (12Mbps) signaling bit rates. It handles data communication task between the Host Computer/USB Bus and the AGE (Download picture and control and upload Frame Buffer). PE design has been already completed, implemented and functionally verified on an FPGA Board. The Project includes also the design, implementation, functional verification and integration of a USB2.0 Protocol-aware Direct Memory Controller (DMAC). A Commercial USB 2.0 Transceiver Chip (PHY), having a UTMI+ Low Pin Interface (ULPI), is used to connect the PE to the USB connector/line. It converts analog signals into digital and vice versa and serial-to-parallel/parallel-to-serial conversion. A Low Dropout (LDO) Voltage Regulator and a XTAL Oscillator, completes the entire GOK System.
2. System Block Diagram
GOK System Integration Project Book
Optical Transport Network (OTN) System Integration
2012
Maayan Moraly
Netanel Gonen
1. Introduction
OTN System Integration Project is a Software/Hardware integration of the new very high bandwidth Networking ITU-T G.709 Standard for Optical Transport Network (OTN) Framer Device. The goal is to deliver a stable, high throughput Framer that combines 4 data ports (sources) into a single data stream, including Overhead Information and deliver data to 4 ports (destinations), adhering to the STD, without mistakes. The challenge is to define and implement a complete System-on-Chip (SoC), having the right SW/HW partitioning to achieve performance and flexibility goals. The OTN Framer Firmware to be executed on a General Purpose Embedded Core (IP) @ 400MHz clock under Real Time Operating System (RTOS), working in conjunction with specific-designed Hardware Accelerators, to cope with the high data rate and to verify correct processing of OTN Frames.
OTN System Integration Project Book
