VLSI lab Research Projects
In addition to its educational mission, BIU VLSI Lab is hosting advanced academic research where the designs implemented by undergraduate students and Lab staff are used as a platform for experimentations. This is later followed by designs availed by real industry. Using in-house full designs prior to engagement with industry has a big advantage. In-house design allows very short cycle from development of theory until real design approval. Moreover, engagement with industry based on in-hose real results makes industry more open for cooperation. The present research activity is focusing on low-power design, mostly by clock gating. We plan later to implement a novel Clock Tree Synthesis supplemented with sophisticated clock gating in layout, up to GDSII. Other research activities related to power supply noise reduction have lately been initiated and will also use BIU backend designs for their validity.
Data-Driven Clock Gating
Decimal Floating Point Unit
Dual Mode Low Power Adder
Security-Oriented System Design
Secure Asynchronous Transmission
Secure Scan Chain
Multi-bit FF
Random Number Generator
Data-Driven Clock Gating
2012
Dvir Shasha
Dov Gropper
Data Driven Clock Gating is a research study by Professor Shmuel Wimer. Its’ main purpose is to reduce power consumption of electronic circuits. It is based on new methods for extensive clock gating, based on statistical models. The project implements the technique described in Professor Wimer’s research on a design in Register Transfer Level (RTL).
Motivation: The increasing demand for low power mobile computing and consumer electronics products has refocused VLSI design in the last two decades on lowering power and increasing energy efficiency. Power reduction is treated at all design levels of VLSI chips. From the architecture through block and logic levels, down to gate level circuit and physical implementation, one of the major dynamic power consumers in the system clock signal, typically responsible for up to 50% of the total dynamic power consumption. Clock network design is a delicate procedure, and is therefore done in a very conservative manner under worst case assumptions. It incorporates many diverse aspects such as selection of sequential elements, controlling the clock skew, the decision of the topology and physical implementation of the clock distribution network.
DDCG Project Book
Decimal Floating Point Unit
2011
Ariel Burg
Hillel Rosensweig
Decimal multiplication is important in many commercial applications including financial analysis, banking, tax calculation, currency conversion, insurance, and accounting. Due to the importance of decimal arithmetic in commercial applications and the potential speedup achievable microprocessors supporting decimal floating-point (DFP) arithmetic are now available.
Further, specifications for decimal arithmetic have been added to the updated IEEE – 754-2008 Standard for Floating-Point Arithmetic. This standard provides a method for computation with floating-point numbers that will yield the same result whether the processing is done in hardware, software, or a combination of the two. The results of the computation will be identical, independent of implementation, given the same input data. Errors, and error conditions, in the mathematical processing will be reported in a consistent manner regardless of implementation.
In this project a decimal floating-point unit that complies with IEEE 754 specifications for decimal Floating point will be designed, implemented and tested.
DFPU Project Book
Dual Mode Low Power Adder
2013
Omry Cohen
Eyal Aberback
Implementing Research Project, targeted to reduce power consumption of a basic Processor's ALU operation – Add. It will be accomplished by designing dual mode Adder - fast/high-power and slow/low-power modes.
The Adder will be incorporated into a 32bits MIPS Processor's ALU and implemented on an FPGA Board. Power saving capabilities will be demonstrated by running industry standard performance benchmark.
Security-Oriented System Design
2013
Lior Hertz
Eitan Miller
Security is a two-fold problem: a. Making the data unreadable to unauthorized people. b. Protecting the Hardware that process the data, from malicious attacks. This project is focused on adding measures to existing Hardware to make it capable identify that it is under attack (with high probability) and act accordingly.
Secure Asynchronous Transmission
2014
Security is a two-fold problem:
a. Making the data unreadable to unauthorized people.
b. Protecting the Hardware that process the data, from malicious attacks.
This project is focused on designing reliable and secure on-chip asynchronous data transfer.
Secure Scan Chain
2014
Implementing Research Project, targeted to protect Data Processing Hardware from malicious attacks, gaining access through the Scan Chain circuit.
The design will provide a secured off-line testing of the circuit.
The secured scan chain circuit will be incorporated into the BIU 32bit MIPS Processor.
The integrated system will undergo security check to verify correct operation / security level.
Multi-bit FF
2014
Implementing Research Project, targeted to reduce power consumption of VLSI Devices.
It will be accomplished by designing 2-bits and 4-bits Flip-Flops (saving in driver), in gate level RTL.
Verify performance and functionality by integrating Data-Driven Clock Gating and Multi-bit Flip-Flops, in BIU 32bit MIPS Processor. Synthesizing the verified Gate-Level RTL Design by replacing regular FF library cells with Multi-bit Flip-Flops.
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Random Number Generator
2014
Implementing Research Project, targeted to design a core that generate random numbers, based on random behavior of halted Buzzer.
It will be accomplished by designing special registers and be tested to verify the randomness of the generated series of bits.
To be implemented on a FPGA Board.
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