VLSI lab Working Environment

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Design and Implementation Tools

Design and Implementation activities are performed by industry standard CAD tools.
Devices and System Integration are performed using the following tools:

  • Cadence Incisive Front-End Design Environment
  • Cadence Encounter Back-End Design Environment
  • VirageLogic/Synopsys 65nm Library and Memory Compiler
  • Altera Quartus II 10.1 Web Edition FPGA Development Environment
  • Xilinx ISE Design Suite 13.2 and PlanAhead 13.2 FPGA Development Environment
  • Jungo WinDriver Development Environment
  • C++, C-Sharp for Software Development
  • Verilog for writing RTL Code, Visio for drawing device/system top-level/Block-Diagram

LAB Equipment / Stations / Servers / etc.

  • 5 Personal Computers
  • 7 Server Terminals
  • 1 RedHat Linux Server (16 Compute Cores) for Cadence Design Tools.
  • 8 Altera FPGA Development Boards - DE2 / DE2-115 / DE3 / DE4
  • 8 Xilinx FPGA Development Boards - ML605 / ATLYS
  • Multimeter