Gain-cell eDRAM Based Cache Memory Optimization for Low-Power Systems

Embedded memories dominate the area, power and cost of modern very large scale integrated systems on chip (VLSI SoCs). Due to process variations, it remains challenging to design reliable energy efficient systems. SRAM has been the traditional choice for embedded memory since it provides high-speed read and write operations and static data retention. However, growing memory capacities have led to significant efforts to replace the relatively large SRAM bit-cell with a smaller alternative. Gain Cell embedded DRAM (GC-eDRAM) has recently been recognized as a possible alternative to traditional SRAM. While GC-eDRAM inherently provides high-density, low static leakage and two ported operation, its limited retention time requires periodic, power-hungry refresh cycles. This drawback is further aggravated in scaled technologies, where increased leakage currents and decreased storage capacities result in faster data deterioration. This faster data deterioration affects not only power consumption because needs to be refreshed the memory more often, but performance as well. Due to the refresh period the memory available to the processor is also reduced. In this thesis new techniques, an algorithm and an architecture are developed to overcome these drawbacks. A new bit-cell level techniques for improving the DRT and read performance are introduced. A new memory array architectural approach to combine static and dynamic RAM for error tolerance applications is suggested. Finally, a novel refresh algorithm that increases the memory availability in an opportunistic manner is presented. 

* This work was carried out under the supervision of Prof. Alex Fish and Prof. Shmuel Wimer,Faculty of Engineering, Bar-Ilan University as part of the research for my Master's Degree.