פיתוח זכרונות מוגנים בפני תקיפות הספק

Power Analysis Resilient Memories

Power analysis attacks have become a serious threat to security systems by enabling secret data extraction using side-channel leakage information. Embedded memories, often implemented with 6T SRAM cells, serve a key component in many of these systems. However, conventional SRAM cells are prone to side-channel power attacks.
In this project, we will develop novel memory structures which are resilient to power analysis attacks at various design hierarchies. The design will be implemented and verified in a deeply-scaled CMOS technology.

דרישות:

Digital Circuits, Digital Integrated Circuits