Frequency Locked Loop Circuit for High Frequency IC Clocks

הרקע לפרויקט:

A stable clock source is one of the most important requirements for integrated circuit designs. Fully integrated on-chip generation of a clock source has become more important as system-on-chip designs have proliferated. More specifically, wireless sensor nodes for Internet-of-Things (IoT) applications have a small form factor and limited board space, making it difficult to integrate crystal oscillators, especially for implantable applications. An on-chip oscillator requires low power consumption and energy per cycle, frequency stability over varying ambient temperatures, long-term stability, and low supply voltage sensitivity. Low oscillator power consumption is important in a system with low activity where the standby current dominates the total power consumption, as is the case with a wake-up timer or a sleep mode timer. An oscillator must also show good frequency stability and resistance to temperature supply voltage and random variations. At low voltage and low power, this becomes even more challenging.

מטרת הפרויקט:

In this project, several novel techniques will be utilized to design an FLL. These techniques involve a combination of analog, digital and device physics concepts. During this work, you will design a novel FLL, all of which will be implemented in a Si IC.

תכולת הפרויקט:

In this project the student will design an FLL using digital and analog techniques. The schematics will be prepared in Virtuoso and simulated. Layout and post-layout simulations will be conducted to verify the circuit performance. This project will include a tapeout and Silicon measurements. The successful conclusion of this project may lead to an academic publication.

קורסי קדם:

768330301 אלקטרוניקה לינארית - חובה
768332501 מעבדה למעגלים אנלוגיים – חובה
8330801 מעגלים אלקטרוניים ספרתיים – חובה
83315 מעבדה מעגלים אלקטרוניים ספרתיים – חובה
768361101 מעגלים משולבים אנלוגיים – מומלץ

מקורות:

1. M. Choi, T. Jang, S. Bang, Y. Shi, D. Blaauw and D. Sylvester, "A 110 nW Resistive Frequency Locked On-Chip Oscillator with 34.3 ppm/°C Temperature Stability for System-on-Chip Designs," in IEEE Journal of Solid-State Circuits, vol. 51, no. 9, pp. 2106-2118, Sept. 2016, doi: 10.1109/JSSC.2016.2586178.
2. A. Djemouai, M. A. Sawan and M. Slamani, "New frequency-locked loop based on CMOS frequency-to-voltage converter: design and implementation," in IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 48, no. 5, pp. 441-449, May 2001, doi: 10.1109/82.938354.
3. D. S. Truesdell, A. Dissanayake and B. H. Calhoun, "A 0.6-V 44.6-fJ/Cycle Energy-Optimized Frequency-Locked Loop in 65-nm CMOS With 20.3-ppm/°C Stability," in IEEE Solid-State Circuits Letters, vol. 2, no. 10, pp. 223-226, Oct. 2019, doi: 10.1109/LSSC.2019.2946767.