ניתוח ותיכנון מעגלי לוגיקת Dual-Mode לשימוש במערכות "חישוב משוערך"
Exploiting Dual Mode Logic for Approximate Computing
The Dual mode logic (DML) family has been proposed to provide low-granularity energy-delay (E-D) optimization in digital designs. In fact, the DML allows on-the-ﬂy change of the operation of the logic gates between two distinct working modes, namely static and dynamic. In the static mode, DML exhibits very low energy consumption at the cost of reduced speed, as compared to standard CMOS logic. Alternatively, DML gates can operate in the dynamic mode with significantly increased speed at the expense of larger energy consumption. This unique feature of the DML logic family could be exploited in the context of Approximate computing. Approximate computing is an emerging design paradigm, which includes the development of processors and programs that exploit the inherent resilience to errors of many applications to relax the design constraints and reduce the power consumption. This project will evaluate the suitability of the DML logic in approximate arithmetic designs such as adders and multipliers.
Digital Circuits, Introduction to Integrated Circuits