פיתוח זיכרון בעל יכולת גילוי ותיקון שגיאות
Embedded Memory with Inherent Error Detection and Correction Capabilities
In accordance with Moore’s Law, the size, density, and power consumption of SRAMs has grown exponentially over the past five decades, often being responsible for over 50% of the total area and static power consumption of modern ASICs. However, technology and voltage scaling increase the error susceptability of these memories, often requiring the integration of high-overhead error-correction-codes (ECCs).
Gain-cell Embedded DRAM are a possible alternative to conventional SRAM due to their smaller size, low leakage and 2-ported operation. However, they require power-hungry refresh cycles to retain their data.
In this project, we will exploit the characteristics of GC-eDRAM to offer low-overhead techniques for error detection and correction in memory arrays.
This work will include optimizations at an architectural and algorithmic levels, verified with analog simulation and synthesis of a digital wrapper, and compared to conventional ECC techniques used in the state-of-the-art.
Digital Circuits, Digital Integrated Circuits