HiPer Consortium Event

שלחו לחבר
24/05/2017 - 15:30 - 08:30הוספה ליומן 2017-05-24 08:30:00 2017-05-24 15:30:00 HiPer Consortium Event Schedule 08:30 – 09:30 Registration and Coffee 09:30 – 09:45 Welcome and HiPer 3rd Year Overview: Ilan Peled, Rafi Retter 09:45 – 10:30 Key Note: Prof. Kaushik Roy, Purdue University 10:30 – 11:30 Expert Panel: VLSI Technologies in the Twilight of Moore’s Law and Beyond: Prof. Kaushik Roy, Purdue University, Dan Kochpatcharin, TSMC, Marco Casale Rossi, Synopsys, Ronen Lovinger, Mellanox 11:30 – 12:00 SoC Lab @ BIU: Yonatan Shoshan,  EnICS 12:00 – 12:20 SoC1 + DAFNA Demonstrations 12:20 – 13:30 Lunch Lectures by Consortium members: Three years major achievements 13:30 – 13:50 Optimal Generation of Multiplier Arrays: Udi Kara, Satixfy 13:50 – 14:10 DAFNA - Scaling GC-eDRAM down to 28nm: Robert Giterman,  EnICS Labs 14:10 – 14:30 Multicore Challenges & Research Directions: Alon Ya’akov, CEVA 14:30 – 14:50 Consortium Achievements in VLSI Verification: Noam Meser, CEVA 14:50 – 15:10 Utilizing Vector Processor DSP Architecture Features for TC Application Speedup: Shlomo Greenberg, BGU http://www.eng.biu.ac.il/enics/cadence-workshop/ מרצהFaculty of Engineering, Bar-Ilan UniversityAffiliationFaculty of Engineering, Bar-Ilan University Faculty of Engineering building הפקולטה למשפטים law.faculty@mail.biu.ac.il Asia/Jerusalem public
מיקום
Faculty of Engineering building
דוא"ל להרשמה
adam.teman@biu.ac.il

Schedule

08:30 – 09:30 Registration and Coffee

09:30 – 09:45 Welcome and HiPer 3rd Year Overview: Ilan Peled, Rafi Retter

09:45 – 10:30 Key Note: Prof. Kaushik Roy, Purdue University

10:30 – 11:30 Expert Panel: VLSI Technologies in the Twilight of Moore’s Law and Beyond: Prof. Kaushik Roy, Purdue University, Dan Kochpatcharin, TSMC, Marco Casale Rossi, Synopsys, Ronen Lovinger, Mellanox

11:30 – 12:00 SoC Lab @ BIU: Yonatan Shoshan,  EnICS

12:00 – 12:20 SoC1 + DAFNA Demonstrations

12:20 – 13:30 Lunch

Lectures by Consortium members: Three years major achievements

13:30 – 13:50 Optimal Generation of Multiplier Arrays: Udi Kara, Satixfy

13:50 – 14:10 DAFNA - Scaling GC-eDRAM down to 28nm: Robert Giterman,  EnICS Labs

14:10 – 14:30 Multicore Challenges & Research Directions: Alon Ya’akov, CEVA

14:30 – 14:50 Consortium Achievements in VLSI Verification: Noam Meser, CEVA

14:50 – 15:10 Utilizing Vector Processor DSP Architecture Features for TC Application Speedup: Shlomo Greenberg, BGU

http://www.eng.biu.ac.il/enics/cadence-workshop/

מרצה
Faculty of Engineering, Bar-Ilan University
Affiliation
Faculty of Engineering, Bar-Ilan University