III–V Semiconductors FinFETs for VLSI Technology
The scaled VLSI CMOS transistors with sub 20 nm channel length are facing fundamental limits like tunneling, short channel effects and drain induced barrier lowering. FinFETs, having better electrostatic control than the planar FETs, can address these fundamental limits. The scaled finFET with sub 20 nm channel length should have fin thickness of less than 10 nm and ratio of fin height / fin pitch larger than 10, to follow the requirements of VLSI systems: excellent electrostatic, high packing density and high current density devices.
III-V semiconductors with high carrier velocity are excellent candidates for VLSI finFETs, and the required nanometer control can be addressed with atomic layer epitaxy grown fins. The atomic layer epitaxy grown fins is a promising technology for manufacturing ultra-tall fins with high packing and high current densities.
Another approach to increase the current density is to populate both Γ and L energy ellipsoids, common for III-V semiconductors, for high carrier and current densities carried by the III-V finFETs. These Γ–L designed III-V finFETs, a few nanometers wide, can have up to 30% more current density than their Si counterparts.
In this talk the two approaches to improve III-V finFETs performances will be discussed together with state of the art planar III-V FET.