A Low Energy Dual-Mode Adder
Abstract: VLSI designs are typically data-independent and as such, they must produce the correct result even for the worst-case inputs. An adder design, in particular, assumes that the execution of an operation must be completed within the allocated number of clock cycles, independently of its operands. While the longest carry propagation of an n-bit adder is n bits, its expected length is only O(log2n) bits. In this paper we present a novel dual-mode adder architecture that considerably reduces the average energy consumed by the adder. In its normal mode the adder targets the O(log2n)-bit average worst-case carry propagation chains, while in its extended mode it accommodates the less frequent O(n)-bit chain. We prove that the dual-mode adder consume minimum energy when it is designed for O(log2n) carry propagation, and present a circuit implementation for such an adder. Dual-mode operation enables voltage scaling of the entire system, potentially supporting further overall energy reduction. The energy-time trade-off obtained when incorporating such adders in ordinary microprocessor’s pipeline and other architectures is discussed.
* This work was carried out under the supervision of Prof. Shmuel Wimer Faculty of Engineering, Bar-Ilan University as part of the research for my Master's Degree.