Clock Gated Multi Bit Flip Flop Design for Low Energy
Abstract—Data-driven clock gating (DDCG) and multi-bit flip-flops (MBFFs) are two effective low-power design techniques. Though commonly used by VLSI designers, those are usually separately treated. MBFF internal circuit design, its multiplicity and its synergy to the flip-flops (FFs) data toggling probabilities have not been studied so far. This work attempts to maximize the energy savings by proposing a DDCG and MBFF combined algorithm, based on FFs data-to-clock toggling ratio. It is shown that to maximize the power savings, the FFs should be grouped in MBFFs in increasing order of their data toggling probabilities. A power savings model utilizing MBFF multiplicities and FFs toggling probabilities is developed, which is then used by the algorithm in a practical design flow. We achieved 17% to 23% power savings in the design of two processors, compared to designs with ordinary FFs.
* This work was carried out under the supervision of Prof. Shmuel Wimer, Faculty of Engineering, Bar-Ilan Universirt as part of the research for Master's Degree.