Clock-Tree Optimization for Power Supply Noise Reduction
Abstract: In today’s process technologies, power supply noise may cause serious clock jitter and circuit malfunction. Noise occurs by the fast and simultaneous voltage switching. A primary contributor to the noise is the clock-tree and the underlying sequential circuits that switch simultaneously, thus causing high current peaks. This work proposes to spread the switching of the clock-tree drivers, while maintaining low skew at the sinks of the tree, where the clocked circuits are connected. The work employs a mix of high threshold voltage (HVT) and weak low threshold voltage (LVT) clock-drivers. The algorithm was implemented in 40 nanometers TSMC process technology, achieving 35% to 70% clock-tree peak current reduction, translated to similar reduction in power supply noise. The proposed method can easily be combined with other existing methods to further reduce the noise.
* This master work was carried out under the supervision of Prof.Shmuel Wimer