Design of column-counter Single-slope ADC for CIS application

הרקע לפרויקט:

Compact digital cameras now require a high pixel count, high imaging performance, and low power consumption. The advantages of a CMOS image sensor are low power and easy system integration with on-chip circuits.

High-speed CMOS image sensors with on-chip ADC have been developed, and the relatively simplified Single-Slope (SS) ADC is widely used in a variety of image sensors. The column-counter is one of the main building blocks of the SS-ADC, and its high-speed operation and low-power consumption operation are essential for meeting the imager requirements.

מטרת הפרויקט:

In this work the student plan to explore the state of-the art column counter architectures and design a high-speed and low power 10-bit column-parallel counter for SS -ADC.

תכולת הפרויקט:

• Literature survey
• Design consideration & analysis.
• Design: schematic, spice simulations, (layout work is pending on available resources).

קורסי קדם:

83313

מקורות:

1. 12-bit Column-Parallel Single-Slope ADCs with Operation-Period-Reduced Time-to-Digital Converters for CMOS Image Sensors, Tokyo, Japan.
2. A Low-power 65/14nm Stacked CMOS Image Sensor, Samsung Electronics, Hwaseong, South Korea.