Advanced dynamic memory bitcells

הרקע לפרויקט:

Gain-cell embedded DRAM (GC-eDRAM) is a dynamic storage technology that presents an alternative to standard SRAM for various applications. In this project, novel circuit techniques will be developed for GC-eDRAM based memories to improve performance, power, and area (PPA) costs.

מטרת הפרויקט:

Characterization of novel GC-eDRAM bitcell topology and physical design of memory array based on it.

תכולת הפרויקט:

This research project will include Virtuoso based simulation in advanced technology nodes, designing the array architecture and implementing it in physical layout

קורסי קדם:

מעגלים משולבים ספרתיים 83-313

דרישות נוספות:

מעגלי ומערכות וי.אל.אס.איי. דיגיטליים - 83-612

מקורות:

1. P. Meinerzhagen, A. Teman, R. Giterman, N. Edri, A. Burg, and A. Fish, Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip. Berlin, Germany: Springer, 2018.
2. Teman A, Meinerzhagen P, Burg A, Fish A (2012) Review and classification of gain cell eDRAM implementations. In: Proc. IEEE Convention of Electrical and Electronics Engineers in Israel (IEEEI), pp 1–5
3. Configurable Multi-Port Dynamic Bitcell with Internal Refresh Mechanism https://ieeexplore.ieee.org/document/8617861
4. A 4T GC-eDRAM Bitcell with Differential Readout Mechanism For High Performance Applications https://ieeexplore.ieee.org/document/10559672