Hidden refresh gain cell (eDRAM)

הרקע לפרויקט:

"This project aims to create a faster CMOS based dynamic memory, based on the gain cell architecture from ENICS lab with hidden refresh.

The aim of this project is to simulate a high-performance CMOS-based dynamic memory using a gain cell architecture with hidden refresh. The design comes from the ENICS lab, and students will be required to use Cadence Virtuoso for comprehensive simulations of the memory system. The focus is on understanding how this memory architecture compares to existing technologies, by evaluating its performance under different conditions."

מטרת הפרויקט:

The goal is to design and simulate a new memory cell.

תכולת הפרויקט:

"The student will need to simulate using virtuoso: behavioral logic, transient response, timing analysis with process variation and corners, designing and simulating the peripheries and compare the results to state of the art solutions.

Deliverables:
A report that includes:
Description of the behavioral logic, transient, timing, and peripheral simulations.
A comparison of your results with state-of-the-art designs.
Observations on the impact of process variations and corner cases.
Clear explanations and discussion of any deviations from expected results.

Simulation files for:
Behavioral Logic
Transient Response
Timing Analysis
Peripheral Design "

קורסי קדם:

מעגלים משולבים ספרתיים 83313

מקורות:

4T Gain-Cell Providing Unlimited Availability
Through Hidden Refresh with 1W1R Functionality

https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=9401416&casa_token…