SRAM Power Reduction and Stability in Nanoscale Era
The continuous device scaling according to Moore's Law has led to the integration of billions of transistors on a single chip, including embedded memory arrays that already comprise over half of the die area of high-end microprocessors, and are expected to keep on growing. However, transistor scaling is accompanied by many secondary effects, such as device variability, mismatch, and high leakage currents. Due to their sheer size and density, these effects highly impede the data stability of large SRAMs, and have made SRAMs the major contributor to the static power component of modern systems. One of the most straightforward and efficient ways to combat this leakage power is through voltage scaling; however, this presents increased variation and depleted noise margins, leading to a loss of stability.
In this talk, I will discuss both the stability of modern SRAM circuits and their power dissipation and present several approaches I have used to try and overcome the inherent design problems. These include alternative SRAM bitcells for low voltage operation, monitoring circuits for low voltage sleep modes, and replacing SRAM with an embedded DRAM alternative.