Enabling 3-D ICs as a Platform for Future VLSI

שלחו לחבר
Boris Vaisband
Engineering Building 1103, Room 329
Department of Electrical and Computer Engineering, University of Rochester, Rochester, NY

TSV-based three-dimensional integrated circuits are an effective platform for heterogeneous integration. Multiple design issues and possible solutions associated with enabling 3-D technology are presented. Design insight into thermal coupling in 3-D integrated circuits through both experiment and simulation is provided, and suggestions to mitigate thermal effects in 3-D ICs are offered. A 3-D test circuit examining thermal propagation within a TSV-based 3-D integrated stack has been designed, fabricated, and tested. To address performance and functional degradation due to high ambient temperatures, a method for modeling the relative thermal interaction among different modules within a 3-D system is introduced. A thermal aware floorplan methodology based on this thermal interaction is proposed. In addition to thermal coupling, models of capacitive noise coupling from an aggressor module to a victim module through the TSVs within heterogeneous 3-D integrated circuits are described. A 3-D noise coupling system is evaluated for isolation efficiency. Technology specific techniques to improve the isolation efficiency within heterogeneous 3-D systems are demonstrated. Additional aspects of noise coupling within TSV bundles are also studied. A hexagonal TSV bundle topology to reduce both coupling noise and area is introduced. The topology exhibits superior symmetry as compared to a classical mesh topology. A comparison between the hexagonal and mesh topologies in terms of area per TSV, capacitive coupling, effective inductance, and shielding characteristics is offered. The hexagonal topology exhibits a reduction of 13% and 7% in, respectively, the area per TSV and capacitive coupling. In addition, a two to three orders of magnitude improvement in effective inductance within the hexagonal topology is observed. Solutions for the primary bottleneck issues in 3-D integration of thermal congestion, noise coupling, and TSV placement are necessary for enabling 3-D ICs as a platform for heterogeneous electronic systems.