Optimal VLSI Delay Tuning by Wire Shielding
Interconnect shielding is used in VLSI designs to prevent noise interference from the cross-coupling capacitance between adjacent signals. Most notably shielded are the clock signals being spread across the entire silicon die, used to synchronize the operation of the underlying digital circuits. This work takes advantage of the shields already present in the design, and uses them to tune the propagation delay of the clock signals, thus eliminating expensive and process variation sensitive dedicated delay buffers. The mathematical properties of the delay incurred by shielding are studied. The problem of obtaining a desired delay with minimum shielding cost is presented and solved by means of the calculus of variations. An analytical solution shows that a square root shield profile is optimal. Since real VLSI technology dictates discrete solution, the best piecewise-constant approximation of the optimal continuous solution is studied. A clock-tree synthesis methodology that uses shields to obtain useful skews at the underlying flip-flops is proposed. The method was tested on an industrial 28nm memory controller design, and confirmed its viability for delivering the required useful skews to flip-flops.
* The work was carried out towards the M.Sc. degree in the Faculty of Engineering, Bar-Ilan University, under the supervision of Prof. Shmuel Wimer.