שיפור שימור מידע בזכרונות מוטמעים בשילוב שיטות אלגוריתמיות/סטטיסטיות
Improving data integrity in embedded memories by applying algorithmic/statistical methods
Gain-cell embedded DRAM (GC-eDRAM) is a memory technology that has been shown to be an interesting alternative to standard SRAM for various applications. One of the drawbacks of this technology is the limited data retention time (DRT) due to parasitic leakage currents. In this project, the students will model the probability of cell failures and explore the possibilities of improving the DRT through algorithmic approaches mixed with circuit design techniques. The project is a research project with both theoretical and implementation components, intended for both Electrical and Computer Engineering students.
Course 83-313 - required. Advantages for computer architecture, probability, and verilog.
The work will include Matlab, and probably Verilog/Virtuoso components.