Gain-Cell eDRAM for Low-Power VLSI Systems-on-Chip

Embedded memories dominate the area, power and cost of modern very large scale integrated (VLSI) systems on chips (SoCs). Furthermore, due to process variations, it has been challenging to design reliable energy-efficient systems. Static random access memory (SRAM) has been the traditional choice for embedded memory since it provides high-speed read and write operations and static data retention. However, the 6-Transistor (6T) SRAM bitcell is relatively large, exhibits several leakage paths, and has dramatically increased failure rates under voltage scaling. Gain-Cell embedded DRAM (GC-eDRAM) has recently emerged as an alternative to conventional embedded memories based on SRAM, as it offers high density, low leakage power consumption, two-ported operation, and full logic-compatibility. The main drawback of GC-eDRAM compared to SRAM is the need for periodic refresh operation due to the dynamic nature of data storage. This presentation will cover several techniques to extend the data retention time of GC-eDRAM, in both circuit and architecture levels. In addition, the design and implementation of novel GC-eDRAM macrocells in both mature and advanced technology nodes will be presented, targeting a large range of applications, ranging from low-power/low-voltage storage arrays, to high-density storage arrays for high performance, potentially error-resilient VLSI systems.

* PhD. research supervised by: Prof. Alex Fish and Dr. Adam Teman