Architectures for Processing in Resistive Memory

שלחו לחבר
Leonid Yavits, Technion
BIU Engineering Building 1103, Room 329

High-performance processing is shifting from the traditional computing centric model used for many decades into a data centric one. This transition is driven by emerging data-intensive applications such as machine learning or bioinformatics, which are no longer dominated by the arithmetic calculations but instead by the handling of large data volumes and the cost of moving data to the locations where computations are performed. In data-centric model, data lives in different storage levels within the memory hierarchy, with processing engines surrounding data and operating on such data without moving it across the system.

I will present a Resistive Associative in-Memory Processor, that functions simultaneously as a storage and a massively parallel SIMD accelerator. It confines the computing to the memory arrays, thus implementing in-data rather than near-data processing. Resistive Associative In-Memory Processor outperforms the fastest state of art accelerators, achieving speedup of 9.7×, 5.1×, 3.5× and 2.9× for k-means, k-nearest neighbors, Smith-Waterman sequence alignment and Long-Short Term Memory (LSTM) Neural Network, respectively.

I will also present RASSA, a novel resistive accelerator for DNA read mapping, a computationally expensive bioinformatics task, required among other for genome assembly. RASSA exploits charge distribution and parallel in-memory processing to reflect a mismatch count between DNA sequences. RASSA implementation of DNA long read pre-alignment outperforms the state-of-art solution, minimap2, by up to 77×.