Examination and Integration of Alternative Digital Design Logic Families into EDA Tools
CMOS logic family is a popular one and used for ICs (integrated circuits) building since the early 60's. This logic is characterized by relatively low static power consumption, rail to rail swing, noise immunity and mainly by its universality and simplicity which enables to implement every logical gate and circuit in designer-friendly way. The main drawbacks of CMOS logic are relatively poor performance and considerable leakage power consumption.
More and more modern applications require both low power consumption and high speed performance; hence there is a need to examine alternative digital logic families, which may provide better performance vs. power consumption trade-off flexibility. Several existing static and dynamic digital logic families introduce reasonable performance vs. power trade-off, but their incorporation into a standard automated digital design flow is challenging at least and requires adaptation in order to fit into off-the-shelf synthesis CAD tools. The compatibility to a standard design flow is a crucial factor, because the entire nowadays digital design domain is generated with a help of Computer Aided Design (CAD) tools, while a fully custom design is a negligible niche.
This work examines integration of alternative digital logic families into automated standard digital design flow, which is completely dominated by a static CMOS. As a background the research reviews automated flow integration challenges of GDI and DML logic families and presents initial results to assess the potential. The main efforts are focused on the DML family, as it shows more potential gain in terms of design metrics and its automation design flow might be further generalized to any dynamic logic family.
This work shows for the first time that DML can be integrated into the standard design flow and optimized by various tools (such synthesis and physical design) to withhold DML design restrictions and utilize DML strengths. A fully standard-tools compatible DML-Flow is achieved by adding crucial yet simple steps. In this work, the gap of DML cell library characterization was filled for the first time while the cell library was fully designed and uniquely characterized for the two unique gate-level-operation of both Dynamic and Static modes. The proposed methodology has been verified on a wide variety of benchmark designs with different gate-count and logic depth. Logic synthesis and in-depth PrimeTime timing analysis showed typical performance improvement of about 10% relatively to static CMOS implementation. Energy reduction of static mode and design foot-print metrics greatly depend on the logic structure of the benchmark: unate logic achieves around 20% average energy saving , while the area is very similar to standard CMOS flow and cell-library, on the other hand, non-monotonic logic implementation expands CMOS area about 30% and consumes just a bit more of stationary power.